CMOS memory margining control circuit for a nonvolatile memory
US4658380A · kind A · utility
8Cited by
4References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 28, 1986 |
| Grant date | Apr 14, 1987 |
| Priority date | — |
| Expiry date | Feb 28, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for enabling off-chip measurement of an on-chip generated reference voltage and for effectuating the memory margin testing of nonvolatile memory cells in wells of a CMOS integrated circuit chip. The circuit is configured to selectively couple off-chip voltages of positive and negative potential to nodes on the chip while avoiding undesired forward biasing of p-n junctions. Control is initiated by varying the functions the input pads perform.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.