Bit line precharge on a column address change
US4658381A · kind A · utility
31Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1985 |
| Grant date | Apr 14, 1987 |
| Priority date | — |
| Expiry date | Aug 5, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit has a plurality of bit line pairs and intersecting word lines with a memory cell located at each such intersection. A column address selects the bit line which is to be accessed and a row address selects the word line which is enabled. Memory cells along an enabled word line cause the bit lines to develop a voltage differential. In response to a change in the row address the bit lines are equalized and precharged. In response to a change in the column address, the bit lines are precharged without being equalized so that the developed voltage differential on the bit lines is maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.