Asynchronous row and column control
US4661931A · kind A · utility
15Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1985 |
| Grant date | Apr 28, 1987 |
| Priority date | — |
| Expiry date | Aug 5, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit has a plurality of bit line pairs and intersecting word lines with a memory cell located at each such intersection. A column address selects the bit line which is to be accessed and a row address selects the word line which is enabled. In response to being selected, a bit line is coupled to a data line. In response to a column address transition, all of the bit lines are decoupled from the data lines while bit lines are precharged. In response to a row address transition, the word lines are disabled while the bit lines are equilibrated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.