Via metallization using metal fillets
US4666737A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 1986 |
| Grant date | May 19, 1987 |
| Priority date | — |
| Expiry date | Feb 11, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for semiconductor manufacture wherein a via is defined and etched through an insulative layer of the device to an underlying conductive region and metal fillets are formed in the corner regions of the via. A conformal metal layer is then deposited onto the device and etched until all metal is removed from the insulative layer surface. Finally, a second metal interconnect layer is deposited onto the device and the desired interconnect pattern is defined. The fillets displace the metal subsequently deposited on the via side surface laterally toward the center of the via, thereby preventing severe self-shadowing problems and improving step coverage of metal into the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.