Decoupling capacitor for pin grid array package
US4667267A · kind A · utility
57Cited by
9References
45Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 1986 |
| Grant date | May 19, 1987 |
| Priority date | — |
| Expiry date | Jul 25, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10704
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
High frequency noise is decoupled from power supplied to a Pin Grid Array (PGA) package by insertion of a decoupling capacitor between the PGA package and printed circuit board. The decoupling capacitor comprises a multi layer capacitive element sandwiched between a pair of conductors and having a plurality of leads extending from each conductor. In accordance with the present invention, the decoupling capacitor is individually dimensioned and configured to fit under a PGA package and correspond to the power and ground pin configuration of that PGA package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.