Method and apparatus for error detection and correction in systems comprising floppy and/or hard disk drives
US4667326A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1984 |
| Grant date | May 19, 1987 |
| Priority date | — |
| Expiry date | Dec 20, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/15
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for generating a check sum and a syndrome for detecting errors in a series of bytes comprising a plurality of stages, each stage comprising a plurality of networks of exclusive OR gates, a memory and an exclusive OR gate for exclusively ORing the outputs of the networks resulting from a byte transmitted therethrough with the results stored in a memory in a previous stage due to a previous byte. Each of the stages and the networks therein correspond to a term in a Reed-Solomon polynomial. Except for differences in the number and construction of the networks in each stage, each of the stages are substantially identical and can be selectively used for detecting single and double burst errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.