Substrate bias generator with power supply control means to sequence application of bias and power to prevent CMOS SCR latch-up
US4670668A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 1985 |
| Grant date | Jun 2, 1987 |
| Priority date | — |
| Expiry date | May 9, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A bias generator circuit includes a first high voltage for biasing a N-well region and a second delayed and lower voltage biasing a source region of a P-channel field-effect transistor so as to increase latch-up immunity. The generator circuit includes a high voltage generator and a multiplier circuit responsive to a power supply voltage for generating a first voltage level for biasing the N-well region. A delay network is responsive to the first voltage for generating a delay voltage. A level detection circuit is responsive to the delay voltage and the power supply voltage for generating a control signal when the delayed voltage reaches a predetermined level. A control device is responsive to the control signal for generating a second voltage for biasing the source region of the P-channel field-effect transistor. The second voltage level is delayed and lower than the first voltage level so that the PN junction is reverse biased to increase latch-up immunity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.