CMOS N-well bias generator and gating system
US4670861A · kind A · utility
33Cited by
4References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 1985 |
| Grant date | Jun 2, 1987 |
| Priority date | — |
| Expiry date | Jun 21, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/146
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for preventing forward biasing of the bit line junctions formed between the N-well and bit lines of a CMOS memory. The system includes a gating system for maintaining the bit line voltage at V.sub.CC /2 whenever the well voltage is less than V.sub.CC. A well regulator and well pump maintain the well voltage at a selected multiple of V.sub.CC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.