Boost word-line clock and decoder-driver circuits in semiconductor memories
US4678941A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 1985 |
| Grant date | Jul 7, 1987 |
| Priority date | — |
| Expiry date | Apr 25, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CMOS boost word-line clock and decoder-driver circuit which can be used for CMOS DRAM's with substrate bias in addition to VDD supply. A boost word-line clock circuit including simple CMOS inverters is used for the word-line boost and the possible voltage overshoot, which usually occurs because of capacitor two-way boost, can be completely eliminated. Also, the circuit can be triggered by a single clock. A high performance decoder circuit is provided in combination with the aforesaid CMOS boost word-line clock circuit, such decoder using NMOS pass-gate in the decoder driver and providing fast word-line boosting. The timing between the decoder and the word-line clock activation is not crucial.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.