Method of manufacturing a heterojunction bipolar transistor having self-aligned emitter and base and selective isolation regions
US4679305A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 1985 |
| Grant date | Jul 14, 1987 |
| Priority date | — |
| Expiry date | Dec 18, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/084
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a heterojunction bipolar transistor comprising the steps of forming a first semiconductor layer of a first conductivity type as a collector on a semiconductor substrate, forming a second semiconductor layer of a second conductivity type as a base on the first semiconductor layer, forming a third semiconductor layer of the first conductivity type as an emitter on the second semiconductor layer, the third and second semiconductor layers constituting a heterojunction, selectively forming a first mask on the third semiconductor layer, ion-implanting ions of an impurity of the second conductivity type into the resultant structure using a first mask, thereby forming an external base region of the second conductivity type extending to the second semiconductor layer, forming a second mask on a side wall of the first mask, and ion-implanting a predetermined material into the resultant structure using the first and second masks, thereby forming a high-resistance layer for isolating the external base region in self-alignment with the emitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.