Graded extended drain concept for reduced hot electron effect
US4680603A · kind A · utility
21Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1985 |
| Grant date | Jul 14, 1987 |
| Priority date | — |
| Expiry date | Apr 12, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a graded, buried spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.