Structure and fabrication of vertically integrated CMOS logic gates

US4680609A · kind A · utility

Assignee

• Nortel Networks Limited · CA

Inventors

• Iain D. Calder · Gatineau, CA
• Thomas MacElwee · Ottawa, CA
• Abdalla Aly Naem · Sunnyvale, US

Key dates

• Filing date: Sep 24, 1984
• Grant date: Jul 14, 1987
• Expiry date: Sep 24, 2004

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/00

Abstract

A vertically integrated CMOS logic gate has spaced semiconductor layers with control gates located between the layers and insulated from them by gate oxide. Transistors formed in one semiconductor layer are vertically aligned with transistors formed in the other semiconductor layer. Pairs of vertically coincident transistors have common control gates and certain of the pairs have integral drain regions. Transistors in one layer are series connected in an open loop configuration and transistors in the other layer are parallel connected in a closed loop configuration. The logic gate function depends on voltages applied to the common control gates and to the open and closed loops. By the vertical integration, a two-input NAND or NOR gate can be made using less area than that required for two simple MOS transistors.