Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide
US4680853A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 1986 |
| Grant date | Jul 21, 1987 |
| Priority date | — |
| Expiry date | May 30, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
Abstract
A high power MOSFET structure consists of a plurality of source cells distributed over the upper surface of a semiconductor chip, with a drain electrode on the bottom of the chip. Each of the source cells is hexagonal in configuration and is surrounded by a narrow, hexagonal conduction region disposed beneath a gate oxide. The semiconductor material beneath the gate oxide has a relatively high conductivity, with the carriers being laterally equally distributed in density beneath the gate oxide. The high conductivity hexagonal channel is formed in a low conductivity epitaxially formed region and consists of carriers deposited on the epitaxial region prior to the formation of the source region. Symmetrically arranged gate fingers extend over the upper surface of the device and extend through and along slits in the upper source metallizing and are connected to a polysilicon gate grid which overlies the gate oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.