Methods for forming lateral and vertical DMOS transistors
US4682405A · kind A · utility
41Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1985 |
| Grant date | Jul 28, 1987 |
| Priority date | — |
| Expiry date | Jul 22, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
Abstract
A transistor is provided which includes an electrical contact (122) formed in a V-shaped groove (118). Because of the unique shape of the electrical contact, a smaller surface area is required for its formation thus rendering it possible to construct a transistor having a smaller surface area. The groove is formed by anisotropically etching an expitaxial layer (102) on a semiconductor substrate (100) using, for example, KOH.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.