Dynamic ram cell with MOS trench capacitor in CMOS
US4688063A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1986 |
| Grant date | Aug 18, 1987 |
| Priority date | — |
| Expiry date | Oct 21, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/665
Abstract
This invention relates generally to Dynamic Random Access Memory (DRAM) cells and more particularly relates to a DRAM cell wherein the storage capacitor of the cell is disposed in a trench formed in a semiconductor substrate. Still more particularly, it relates to a DRAM cell wherein at least a portion of the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench capacitor forms the other electrode of the storage capacitor. The DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the substrate. The well itself is formed in a lightly doped portion of the substrate and may be n or p-type conductivity with the other portions of the cell having conductivity types appropriate for devices fabricated in the CMOS environment. The trench capacitor extends from the surface of the well through the well and lightly doped substrate portion into the heavily doped portion of the substrate. The electrode disposed in the trench is directly connected to the source/drain of the access transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.