High voltage decoder
US4689504A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1985 |
| Grant date | Aug 25, 1987 |
| Priority date | — |
| Expiry date | Dec 20, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high voltage CMOS decoder and level translator for use in conjunction with EPROMS and EEPROMS utilizes additional series coupled field effect transistors maintained in an on condition so a to prevent the voltage across the pull-up and pull-down field effect transistors from exceeding their break down voltages. For example, in addition to a pull-up P-channel field effect transistor and a pull-down N-channel field effect transistor in the output inverter circuit, additional P-channel and N-channel field effect transistors are coupled in series between the pull-up and pull-down transistors to maintain the voltage across the pull-up and pull-down transistors from exceeding there breakdown voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.