Semiconductor memory device
US4689770A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1985 |
| Grant date | Aug 25, 1987 |
| Priority date | — |
| Expiry date | Oct 28, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An LSI semiconductor memory device in which errors in reading out memory cells connected to outermost bit lines of a memory cell array of the device are substantially eliminated. In accordance with the invention, this is done by making capacitances associated with the bit lines of respective ones of the memory cell array substantially equal to one another. To accomplish this, the configuration of an inside portion of wiring other than the bit lines of the array is made the same as that of the bit lines, and the distance between the outermost bit line and the other wiring is made equal to the distance between adjacent ones of the bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.