Interlayer dielectric process
US4690746A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1986 |
| Grant date | Sep 1, 1987 |
| Priority date | — |
| Expiry date | Feb 24, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for producing a film over a topologically non-planar surface of a material which has a sputter etch rate which is higher in a direction parallel to the plane of the wafer than in a direction perpendicular to the plane of the wafer. Key steps in the process include first, depositing the material by plasma enhanced chemical vapor deposition while simultaneously sputter etching it. Then second, sputter etching the material. Using this two step process, a substantially conformal or sloped film is produced by repeating the steps consecutively until the desired thickness is obtained. The film can then be substantially planarized if desired, by an extended sputter etch to selectively remove material having a sloped surface rather than a flat surface, since the etch rate is higher parallel to the plane of the wafer than perpendicular to the wafer. If a thicker planar surface is desired, additional material can then be deposited by steps of simultaneous plasma chemical vapor deposition and sputter etch, or by consecutive steps of simultaneous plasma deposition and sputter etch followed by sputter etching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.