Semiconductor device having an arrangement for preventing operational errors
US4691304A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 1985 |
| Grant date | Sep 1, 1987 |
| Priority date | — |
| Expiry date | May 30, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/07
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
This invention relates to a semiconductor device formed on a semiconductor chip which is provided with at least a voltage transformation arrangement for transforming an external power supply voltage into an internal power supply voltage. At least a portion of circuits formed in the chip operate by using the internal power supply voltage rather than the external power supply voltage. Semiconductor devices, in particular DRAMs (dynamic random access memories), in which said internal power supply voltage is supplied are controlled so that the starting time of the internal power supply voltage at the moment of the switch-on of the external power supply is later than the starting time of the external power supply voltage, and/or the time necessary for the internal power supply voltage to increase to a predetermined operational level at said moment is longer than that required for said external power supply voltage to increase to a predetermined operational level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.