Selectable multi-input CMOS data register
US4692634A · kind A · utility
11Cited by
4References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 28, 1986 |
| Grant date | Sep 8, 1987 |
| Priority date | — |
| Expiry date | Apr 28, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS data register includes a master stage and a slave stage. The master stage is formed of first transfer gates and first storage devices. The slave stage is formed of second transfer gates, second storage devices and third transfer gates. The transfer gates and storage devices are formed of MOS transistors of one conductivity which decreases layout complexity and reduces the amount of chip area required. The data register is formed of a fewer number of transistor components, thereby reducing the loading on the clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.