Semiconductor memory
US4694428A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1985 |
| Grant date | Sep 15, 1987 |
| Priority date | — |
| Expiry date | Oct 21, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory, a memory cell array is divided into a plurality of sub arrays in a direction perpendicular to word lines. In each sub array sub word lines and bit lines are disposed to intersect each other and memory cells are disposed at all their intersections. Two different sub arrays constitute a unit cell array. The sub word line connected to a cell transistor in one of or the first the sub arrays of the unit cell array is connected to a first main word line and a second main word line which is not connected to the cell transistor in the first sub array is passed therethrough for connection with the sub word line of the other or second sub array in the unit cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.