Method for manufacturing a semiconductor integrated device including bipolar and CMOS transistors

US4694562A · kind A · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Hiroshi Iwasaki · Yokohama, JP
• Shintaro Ito · Tokyo, JP

Key dates

• Filing date: Oct 31, 1986
• Grant date: Sep 22, 1987
• Expiry date: Oct 31, 2006

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0109

Abstract

A semiconductor integrated device (CBi-CMOS) is disclosed wherein both CMOS transistors and a vertical npn and pnp transistor are formed in a single semiconductor substrate and a latch up phenomenon in the CMOS is prevented. A method of manufacturing the CBi-CMOS is also disclosed. In the CBi-CMOS, four elements, that is, an n-MOSFET, a p-MOSFET and npn and pnp vertical transistors are formed in an n-type epitaxial silicon layer formed on a p-type silicon substrate. The n-MOSFET is formed in a p-well which has a p.sup.+ -type buried region. In the element region of the p-MOSFET, an n.sup.+ -type buried region is also formed. In the element regions of the npn and pnp vertical transistors, a first p.sup.+ -type isolation diffusion region is selectively formed. And an n.sup.+ -type buried region is selectively formed both in these element region of the npn and pnp vertical transistors. In the element region of the npn transistor, the vertical npn transistor is formed using the n-type region surrounded by the first p.sup.+ -type isolation diffusion region as a collector. In the element region of the pnp transistor, a p.sup.+ -type buried region is formed on the n.sup.+ -type buried reg…