Memory architecture with sub-arrays
US4698788A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1985 |
| Grant date | Oct 6, 1987 |
| Priority date | — |
| Expiry date | Jul 1, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static RAM has a plurality of sub-arrays arranged in rows and columns, each sub-array having word lines running the length of the sub-array in a top to bottom direction, and having bit lines running the width of the sub-array in a left to right direction, and having a word line driver for enabling a selected word line in response to receiving a row select signal corresponding to the selected word line; a global row decoder for providing the row select signals as determined by row address signals; a first plurality of column pre-decoders for performing a partial decode of data provided on the bit lines of a first of the rows of sub-arrays, each column pre-decoder corresponding to a particular sub-array; a second plurality of column pre-decoders for performing a partial decode of data provided on the bit lines of a second of the rows of sub-arrays, each column pre-decoder corresponding to a particular sub-array; and a plurality of sense amplifiers for sensing the output of the first and second column decoders. The static RAM has an architecture characterized by the memory having a top side, a bottom side, a left side, and a right side; the rows of sub-arrays running from left to ri…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.