Programmable, asynchronous logic cell and array
US4700187A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 1985 |
| Grant date | Oct 13, 1987 |
| Priority date | — |
| Expiry date | Dec 2, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17752
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An asynchronous logic cell and a two- or three dimensional array formed of such cells. Each cell comprises a number of exclusive-OR gates, Muller C-elements and programmable switches. The logic cell is reprogrammable and may even be reprogrammed dynamically, such as to perform recursive operations or simply to make use of hardware which is temporarily idle. Programming is accomplished by setting the states of the switches in each cell. A user-friendly programming environment facilitates the programming of the switches. The array can be used to implement any circuit capable of being modelled as a broad class of Petri Nets. Configurations for (i.e., programs for setting cell switches to create) circuit blocks such as adders, multiplexers, buffer stacks, and so forth, may be stored in a library for future reference. With an adequate library, custom hardware can be designed by simply mapping stored blocks onto chips and connecting them together. Further, because the array is regular and switch settings can produce logical wires, crossovers, connections and routings running both "horizontally" and "vertically", it is in general possible to "wire around" defective elements. If a large wa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.