Method of forming trench isolation in an integrated circuit
US4700464A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Oct 15, 1984 |
| Grant date | Oct 20, 1987 |
| Priority date | — |
| Expiry date | Oct 15, 2004 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/978
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.