Two transistor DRAM cell and array
US4704705A · kind A · utility
16Cited by
3References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 19, 1985 |
| Grant date | Nov 3, 1987 |
| Priority date | — |
| Expiry date | Jul 19, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two transistor Dynamic Random Access Memory Cell and Array. Use of two pass transistors in series for the cell provides numerous additional capabilities for the DRAM array, and, in the preferred embodiment, provides bitline segment multiplexing, so that the sense amplifier pitch can be increased while the bitline capacitance as seen by the sense amplifier and by the memory cell is reduced. To accomplish this, the parasitic capacitance of the node between the two series pass transistors is kept to a minimum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.