Memory device with interconnected polysilicon layers and method for making
US4706102A · kind A · utility
6Cited by
8References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 7, 1985 |
| Grant date | Nov 10, 1987 |
| Priority date | — |
| Expiry date | Nov 7, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device, based upon a field effect transistor having a floating gate is constructed for use in a silicon integrated circuit array of similar memory devices. The memory device includes only two polysilicon layers, a portion of each polysilicon layer being connected to each other through a via hole in an intervening silicon dioxide layer to form the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.