Semiconductor device fabrication process
US4708768A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1987 |
| Grant date | Nov 24, 1987 |
| Priority date | — |
| Expiry date | Mar 10, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device fabrication process comprising the following sequential steps: PA0 Sequential formation of an oxide layer and first layer of masking material resistant both to oxidation (particularly preventing the action of oxidants, such as water vapors and O.sub.2) and heat, on a principal plane of semiconductor substrate; PA0 Patternwise removal of these two layers in overlapping positions to form wells with the above semiconductor substrate exposed at bottom; PA0 Selective removal of the above oxide layer only around the wells thus formed to leave recesses; PA0 Deposition of the second layer of masking material resistant both oxidation and heat on the exposed surfaces of semiconductor substrate at the bottom of the above wells and in the recesses that are left after the above selective removal of oxide layer; PA0 Removal of the above second layer of masking material from the bottom of wells with the masking material left in the above recesses; and PA0 Selective oxidation of exposed surfaces of above semiconductor substrate under masking with the first and second layers of masking material that remain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.