Semiconductor memory device
US4710789A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1986 |
| Grant date | Dec 1, 1987 |
| Priority date | — |
| Expiry date | Dec 3, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device, memory cells of a first column each comprising an N-channel FET are connected to a first bit line, and memory cells of a second column each comprising a P-channel FET are connected to a second bit line. The first bit line and the second bit line are connected to complementary terminals of a sense amplifier to form a folded-bit line pair. A work line is connected to the gate of the N-channel FET of one of the memory cells of the first column and to the gate of the P-channel FET of one of the memory cells of the second column. The word line is selectively provided with a first voltage to make conductive the N-channel FET connected thereto and to make nonconductive the P-channel FET connected thereto, or a second voltage to make conductive the P-channel FET connected thereto and to make nonconductive the N-channel FET connected thereto, or a third voltage to make nonconducitve both the N-channel FET and the P-channel FET connected thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.