Method and apparatus for validating prefetched instruction
US4710866A · kind A · utility
57Cited by
5References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1986 |
| Grant date | Dec 1, 1987 |
| Priority date | — |
| Expiry date | Oct 7, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and data processing system for validating prefetch instruction. The system includes an instruction unit, an n-stage pipeline which provides data segments representing instruction words from a memory to the instruction unit. The system further includes a circuit for prefetching instruction words to be executed subsequently to a presently executing instruction and a circuit for verifying the validity of the prefetched instruction word prior to execution thereof by the execution unit, and a circuit for causing the instruction unit to a fault condition only when the execution of an invalid instruction is begun.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.