Well mask for CMOS process
US4713329A · kind A · utility
9Cited by
27References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1985 |
| Grant date | Dec 15, 1987 |
| Priority date | — |
| Expiry date | Jul 22, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0191
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming CMOS transistors with self-aligned field regions. First and second spaced apart areas are provided on a silicon substrate. A masking member is formed protecting the first of said areas and exposing the second. The exposed area is doped with a p-type material which is driven in to form a p-well. The same region is again doped with additional p-type material after which the CMOS transistors are fabricated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.