Low offset voltage follower circuit
US4714845A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 1986 |
| Grant date | Dec 22, 1987 |
| Priority date | — |
| Expiry date | Nov 28, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/505
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low offset voltage follower circuit includes substantially identical first and second N-channel MOS transistors having their source electrodes connected to a negative terminal of a supply voltage source via a third N-channel MOS transistor whose gate electrode is connected to a first reference voltage, and having their drain electrodes respectively connected to a positive terminal of the supply voltage source via fourth and fifth P-channel MOS transistors whose gate electrodes are connected to a second reference voltage. The gate electrode of the first transistor forms an input terminal of the follower circuit and the gate and drain electrodes of the second transistor are connected together to form an output terminal of the follower circuit. The follower circuit further includes a sixth P-channel MOS transistor having its source, gate and drain electrodes respectively connected to the drain electrodes of the first transistor and the source electrodes of the first and second transistors and the negative terminal of the supply voltage source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.