Quad processor
US4715921A · kind A · utility
116Cited by
6References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1986 |
| Grant date | Dec 29, 1987 |
| Priority date | — |
| Expiry date | Oct 24, 2006 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S414/137
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention includes plural plasma etching vessels and a wafer queuing station arrayed with a wafer transfer arm in a controlled environment. Wafer processing in each vessel is regulated by a state controller for processing a plurality of wafers from a single cassette, contained within the vacuum environment of the plural plasma etching vessels and wafer queuing station, to provide an orderly and efficient throughput of wafers for diverse or similar processing in the plural vessels. In this manner a wafer can be processed as soon as a vessel becomes available.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.