Streamlined digital signal processor
US4718057A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1985 |
| Grant date | Jan 5, 1988 |
| Priority date | — |
| Expiry date | Aug 30, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13405
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An all-digital signal processor (DSP) is disclosed which performs pulse code modulation (PCM) coding and decoding (CODEC) filter operations for both received and transmitted signals, among other functions. A user can access various programmable registers via the microprocessor to specify parameters used in the execution of programs by the DSP. Two 19-bit wide bidirectional data busses are provided for time-division multiplexed communication between various elements, which include a random access memory (RAM), an arithmetic-logic unit (ALU), and an interface to a receive-side analog-to-digital (A/D) converter and a transmit-side digital-to-analog (D/A) converter. A programmed logic array (PLA) executes microcode which controls the processing of signals by the ALU section. A variety of other operations can be performed under control of the PLA such as generation of dual-tone multi-frequency (DTMF) signals commonly used in telecommunications. The architecture of the DSP provides a number of user-accessible registers for the storage of parameters and coefficients used in the generation of the DTMF signals, in the CODEC filtering, and in the compression and expansion of signals. The des…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.