Process for forming semiconductor device having multi-thickness metallization
US4718977A · kind A · utility
13Cited by
7References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1985 |
| Grant date | Jan 12, 1988 |
| Priority date | — |
| Expiry date | Sep 6, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structure and method for metallization patterns of different thicknesses on a semiconductor device or integrated circuit. The improved structure and method utilizes three layers of metal in order to reduce the required number of processing steps. One preferred embodiment entails a single metal deposition sequence followed by two etch steps, while a second embodiment, suitable for thicker metallization, requires only two depositions and two etch steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.