CRC calculation machine with concurrent preset and CRC calculation function
US4720831A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 1985 |
| Grant date | Jan 19, 1988 |
| Priority date | — |
| Expiry date | Dec 2, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant byte of the checksum register. A byte wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock. Preset logic for forcing all logic 1's into the data inputs of the first row of shifting links is provided such the machine can be preset during the first clock cycle of the CRC calculation. Several different architectures are disclosed for allowing separate calculation of CRC bits on a header packet and a data packe…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.