Determination of testability of combined logic end memory by ignoring memory
US4726023A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 1986 |
| Grant date | Feb 16, 1988 |
| Priority date | — |
| Expiry date | May 14, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of bounding, from above and below, the probability of uncovering a fault in a logic portion of an integrated circuit having embedded memory. The circuit must be designed according to a specified set of design rules. Then one or more probabilities of fault exposure is calculated for a modified system with the memory portion removed, with its inputs directly connected to its outputs. This probability can be related, by provided relations, to upper and lower bounds of the fault exposure in the unmodified system. The relationships rely upon how the logic portions process given test vectors to control the unremoved memory portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.