Paged memory management unit which locks translators in translation cache if lock specified in translation table
US4727485A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 1986 |
| Grant date | Feb 23, 1988 |
| Priority date | — |
| Expiry date | Jan 2, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system, a paged memory management unit (PMMU) translates logical addresses provided by a processor to physical addresses in a memory using translators constructed from page descriptors comprising, in part, translation tables stored in the memory. The PMMU maintains a set of recently used translators in a translator cache. In response to a particular lock value contained in a lock field of the page descriptor for a particular page, the PMMU sets a lock indicator in the translator cache associated with the corresponding translator, to preclude replacement of this translator in the translator cache. A lock warning mechanism provides a lock warning signal whenever all but a predetermined number of the translators in the cache are locked. In response, the PMMU can warn the processor that the translator cache is in danger of becoming full of locked translators. Preferably, the PMMU is also inhibited from locking the last translator in the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.