System for addressing a multibank memory system
US4727510A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 1985 |
| Grant date | Feb 23, 1988 |
| Priority date | — |
| Expiry date | May 24, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The preferred embodiment shown involves forming the memory system of B memory banks, where B is preferably a prime number, but may be a nonbinary number, i.e., B=2.sup.X, where X is a positive integer, and where the requested address=(Q+R)B. The address translation system for each requestor seeking access to the memory system includes a ROM and an adder. The ROM is comprised of two ROMs, Q ROMa and Q ROMb. ROMb stores in successive memory locations a first portion Qb of the memory system address and Q ROMa stores in successive memory locatins a second portion Qa of the memory system address. An adder sums the data, Qa+Qb, stored in the addressed memory locations of Q ROMa and Q ROMb while Q ROMa stores in successive memory locations a Bank R portion that specifies the one of the B banks in which the sum Qa+Qb addresses the selected memory address in the selected memory bank of the memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.