Fabrication method for forming a self-aligned contact window and connection in an epitaxial layer and device structures employing the method
US4728623A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1986 |
| Grant date | Mar 1, 1988 |
| Priority date | — |
| Expiry date | Oct 3, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/373
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication process for providing an epitaxial layer on a silicon substrate and over predefined insulator-capped islands which forms a self-aligned contact window in the epitaxial layer. Application of the method to a three-dimensional dynamic random access memory (DRAM) device structure is shown, with an access transistor formed in monocrystalline silicon stacked on top of a trench capacitor. A fabrication method therefor is shown wherein the contact window for the source-to-trench connection is formed by self-aligned lateral epitaxial growth, followed by a contact-connection formation step using either a second epitaxial growth or a CVD refill and strapping process. The invention can be further applied to other device structures using the described principles, and more specifically to an inverter structure having the driver device stacked over the load-resistor as another example, which can be used as a basic building circuit unit for logic circuits and static-RAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.