CMOS circuit having a reduced tendency to latch
US4728998A · kind A · utility
8Cited by
6References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 30, 1986 |
| Grant date | Mar 1, 1988 |
| Priority date | — |
| Expiry date | Jul 30, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/854
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The tendency of a CMOS circuit to latch up is reduced by implanting ions of germanium or tin into the source and drain regions of the circuit. The low energy gap of these ions lowers the band gap of the source and drain regions, which in turn inhibits their ability to inject carriers into the substrate and well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.