Method and apparatus for improved metal-insulator-semiconductor device operation
US4729005A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1986 |
| Grant date | Mar 1, 1988 |
| Priority date | — |
| Expiry date | Jul 31, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/111
Abstract
An improved method and apparatus for reducing edge field enhancement in semiconductor devices such as metal-insulator-semiconductor devices is disclosed. The method comprises the step of biasing a buffer gate which overlies an insulation layer and an area of a substrate in which it is desired to reduce the edge field enhancement at a voltage exceeding the flatband voltage so that a buffered zone is created in the substrate. The apparatus consists of a substrate, a plurality of insulating layers overlying the substrate, at least one gate electrode formed on one of the insulating layers and a buffer gate formed on a second of the insulating layers. When the gate electrode is biased so that a potential well is formed in the substrate, the buffer gate is simultaneously biased so that a buffered zone which adjoins the potential well is formed. This buffered zone results in a decrease in the edge field enhancement observed at the edge of the potential well below the gate electrode and allows the apparatus of the invention to operate in an improved fashion. The method and apparatus of the invention may be incorporated into imaging systems, such as infrared imaging systems, with increased …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.