Logic analyzer
US4730314A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 1985 |
| Grant date | Mar 8, 1988 |
| Priority date | — |
| Expiry date | Nov 12, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3177
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A state analysis section which loads first input data into a first data memory for each change in state of the data and a timing analysis section which loads second input data into a second data memory with a fixed period are provided. The loading intervals of the first input data are measured by a data interval measuring circuit and each measured data loading interval is stored in a data loading interval memory. When the first and second input data are detected to match preset data in first and second trigger detectors, respectively, the detected outputs are delayed by first and second delay means, and by the outputs of the first and second delay means, the first and second data memories are stopped from the data loading thereinto. The time difference between the stopping of the data loading into both the data memories is measured by a time difference measuring circuit and the measured time difference is stored in a time difference memory. When one of the data stored in one of the first and second data memories is specified by specifying means, data in the other data memory corresponding to the point of time at which the specified data was loaded is detected using the data loading…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.