BiCMOS process having narrow bipolar emitter and implanted aluminum isolation
US4734382A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 20, 1987 |
| Grant date | Mar 29, 1988 |
| Priority date | — |
| Expiry date | Feb 20, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bipolar/CMOS process includes bipolar transistors having emitters formed in less than a minimal masking dimension. An opening is formed through a polycrystalline silicon layer deposited on a silicon substrate. After coating the sides of the opening with silicon dioxide, the intrinsic base region of the bipolar transistor and the emitter region are implanted. The extrinsic base is formed by outdiffusion from the polycrystalline silicon layer. The structure includes an epitaxial layer which is more strongly doped below its surface than at its surface to enhance the performance of CMOS transistors formed therein. Additionally, the bipolar and complementary MOS transistors are self-aligned to each other by the manner in which the buried layers are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.