Decoupling capacitor for surface mounted leadless chip carriers, surface mounted leaded chip carriers and Pin Grid Array packages
US4734818A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1987 |
| Grant date | Mar 29, 1988 |
| Priority date | — |
| Expiry date | Mar 19, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10704
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
High frequency noise is decoupled from power supplied to Pin Grid Array (PGA), surface mounted leaded chip carrier and surface mounted leadless chip carrier packages by insertion of a decoupling capacitor between the PGA or leaded chip carrier package and printed circuit board; or by mounting the decoupling capacitor over a leadless chip carrier package. The decoupling capacitor comprises a multi layer capacitive element sandwiched between a pair of conductors and having a plurality of leads extending from each conductor. In accordance with the present invention, the decoupling capacitor is individually dimensioned and configured to fit under a PGA or leaded chip carrier package, or over a leadless chip carrier package; and correspond to the power and ground pin or lead configuration of that PGA, surface mounted leaded chip carrier and surface mounted leadless chip carrier package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.