Decoupling capacitor for surface mounted leadless chip carrier, surface mounted leaded chip carrier and pin grid array package
US4734819A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1987 |
| Grant date | Mar 29, 1988 |
| Priority date | — |
| Expiry date | Mar 19, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Several embodiments of a decoupling capacitor are described which incorporate at least one multilayer capacitive element and which utilize metallized dielectric (i.e., ceramic) substrates rather than a pair of conductors. Also, several types of multilayer ceramic capacitor elements are disclosed which provide a low induction parallel-plate type capacitive structure. The decoupling capacitor assemblies of the present invention are specifically sized and configured so as to be either received in the space directly below the integrated circuit chip and between the downwardly extending pins of a PGA package or "leaded" chip carrier package or to be mounted directly over a "leadless" chip carrier package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.