Semiconductor memory
US4736344A · kind A · utility
22Cited by
3References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 25, 1986 |
| Grant date | Apr 5, 1988 |
| Priority date | — |
| Expiry date | Mar 25, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A refresh arrangement is provided for a dynamic RAM wherein each time a refresh address counter performs a predetermined plurality of steps of increment operations, an address switching circuit is switched to specified refresh addresses held in an address storage circuit to provide addresses of memory cells having inferior data retention times. In this way the memory cells with inferior data retention times can be refreshed much more frequently than memory cells with normal data retention times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.