Memory tester having concurrent failure data readout and memory repair analysis
US4736373A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 1981 |
| Grant date | Apr 5, 1988 |
| Priority date | — |
| Expiry date | Aug 3, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory tester for testing a matrix of memory elements, such matrix having spare rows and columns of memory elements to be used for repair of the memory under test. The memory tester tests the memory matrix to derive failure data and stores the failure data in corresponding rows and columns in a second memory matrix. Failure data in the second memory is scanned, in a first pass, row-by-row and during the first pass scan when the number of failures in any row exceeds the number of spare columns that row is flagged for replacement. Next, in a second pass, the columns of failure data are scanned column-by-column and during the second pass when the number of failures in any column exceeds the number of spare rows, that column is flagged for replacement. If, during either of the first or second pass, the number of flagged rows or columns, respectively, exceeds a certain number, such as the spare rows or columns, that pass is interrupted and the analysis jumps to the next pass. After all spare rows and columns are used, detection of a subsequent failure flags the memory under test as non-repairable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.