Semiconductor memory
US4739497A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1984 |
| Grant date | Apr 19, 1988 |
| Priority date | — |
| Expiry date | Sep 17, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory is provided which includes a plurality of data lines, a plurality of word lines which are arranged so as to intersect the plurality of data lines, and a plurality of memory cells which are respectively disposed at intersection points between the plurality of data lines and the plurality of word lines. A row decoder selects at least one from among the plurality of word lines, while a column decoder generates a signal for connecting one of the plurality of data lines to an input/output line. A plurality of wiring leads are also provided which are formed of a conductor layer different from conductor layers constituting the plurality of data lines and the plurality of word lines and which are arranged so as to intersect the plurality of data lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.