Cache disable for a data processor
US4740889A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1986 |
| Grant date | Apr 26, 1988 |
| Priority date | — |
| Expiry date | Jul 14, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor is adapted for operation with a memory containing a plurality of items of operating information for the data processor. In addition a cache stores a selected number of all of the items of the operating information. When the cache provides an item of operating information, the memory is not requested to provide the item so that a user of the data processor cannot detect the request for the item. A disable circuit is provided to prevent the cache from providing the item when a signal external to the data processor is provided. Consequently, a user, with the external signal, can cause the data processor to make all of its requests for items of operating information to the memory where these requests can be detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.